This invention relates generally to digital signaling. More particularly, this invention relates to circuits for controlling edge rates of digital signals.
Edge-rate control circuits are circuits for controlling the rate at which signals transition between digital levels. Such circuits are useful, for example, for providing adjustable delays, slew rates and duty cycles. Prior art edge-rate control circuits typically operate in either a fast mode or a slow mode according to the state of a control input. In a fast mode, the edge rate of the signal being controlled is relatively fast, speeding transition of the signal from one digital level to another. In a slow mode, the edge rate is relatively slow, delaying transition of the signal between digital levels.
Prior art edge-rate control circuits generally fall into one of two categories: variable capacitance circuits and variable drive strength circuits. FIG. 1A illustrates a prior art edge-rate control circuit 20 of the variable capacitance type. The output of an inverter 21 is loaded by a capacitive element 22, the capacitance of which is controlled by the output of an inverter 24. When the enable input to the inverter 24 is in a first state, a relatively large capacitance is formed by the capacitive element 22, resulting in significant charge diversion to the capacitive element 22 and reducing the edge rate of the output signal on line 23. Conversely, when the enable input is in a second state, a relatively small capacitance is formed by the capacitive element 22, increasing the edge rate of the signal output by the inverter 21.
Capacitive element 22 is typically formed by: a metal oxide semiconductor (MOS) transistor with the gate terminal 22A coupled to the output of the inverter 21 and the body terminal 22B coupled to the output of the inverter 24. The capacitance formed between the gate and body is a function of the potential across the gate and body terminals as shown in FIG. 1B. Thus, when the potential between the gate and body terminals is high, a relatively high capacitance is formed. Conversely, when the potential between the gate and body is low, a relatively low capacitance is formed. One disadvantage of the edge-rate control circuit 20 is that the MOS transistor 22 typically adds some minimum amount of capacitance (CMIN in FIG. 1B) even when the potential between the gate and body terminals is low. Thus, even the fast mode of the edge-rate control circuit 20 is slower than the edge rate that could be achieved if the MOS transistor 22 was omitted.
FIG. 1C illustrates another disadvantage of the edge-rate control circuit 20: asymmetric delay of rising and falling edges relative to a midpoint voltage 18. The input, output and enable signals shown in FIG. 1C refer to the input, output and enable signals for the circuit 20 of FIG. 1A. As shown, the output lags the input by a time tFAST while the enable signal is deasserted. Time tFAST is a combination of the propagation delay through the inverter 21 and the delay caused by the relatively small capacitance on capacitor 22 (CMIN).
When the enable signal is asserted, the body potential of MOS transistor 22 becomes low so that, as the output signal rises, the capacitance of the MOS transistor 22 is increased. Thus, the rise time of the output signal slows as the capacitance increases. This is reflected in the waveform of FIG. 1C wherein the signal initially has a relatively short rise time from the low potential to the midpoint potential 18 and a longer rise time from the midpoint potential 18 to the high potential.
The fall time of the output signal starts out relatively slowly due to the increased capacitance of the MOS transistor, resulting in a relatively long fall time, tFD, from the high potential to the midpoint potential 18. Because transition of the output signal is detected when or shortly after the signal crosses the midpoint potential, the time required for the output signal to transition to the midpoint potential is representative of the output signal delay time for many applications. Thus, the increased capacitance in the MOS transistor when the output signal is high results in asymmetric delays in the rising and falling edges of the output signal, as indicated by the difference between tRD and tFD in FIG. 1C.
FIG. 2 illustrates a prior art edge-rate control circuit 27 of the variable drive strength type. A tri-state inverter 19 coupled in parallel with inverter 21 is either tri-stated or enabled according to the state of an enable signal. When the tri-state inverter 19 is enabled (fast mode), additional current is available to charge the lumped capacitance CL, speeding the overall rise time of the output signal. When the tri-state inverter 19 is disabled (slow mode), reduced current is available to charge the lumped capacitance CL, slowing the rise time of the output signal. One disadvantage of the circuit 27 is that the tri-state inverter 19 itself contributes to the lumped capacitance, CL, so that, even in fast mode, the circuit 27 still provides a slower edge rate than could be obtained if the tri-state inverter 19 is omitted.
In view of the foregoing, there is a need in the art for an improved technique for controlling edge rates of digital signals.
The apparatus of the invention is a circuit to control the edge rate of a digital signal. The circuit includes a conductor to carry a digital signal. A first capacitive component has a first node and a second node, with the second node being coupled to the conductor. A first phase control circuit has a first input node coupled to the conductor, a second input node to receive a first enable signal and an output node coupled to the first node of the first capacitive component. The first phase control circuit processes the digital signal from the conductor and the first enable signal to produce a control signal at the output node to control the edge rate of the digital signal. The first phase control circuit produces the control signal in one of at least two different phase relationships with the digital signal according to a state of the first enable signal. The control signal may be in phase with the digital signal or complementary to the digital signal.
The method of the invention operates to selectively control the edge rate of a digital signal. The method includes the step of combining a digital input signal with an enable signal to produce an edge rate control signal. A capacitive component is operated in response to the edge rate control signal such that the capacitive component selectively controls the edge rate of the digital input signal.
The technique of the invention facilitates the implementation of a spectrum of edge rate transition values. In addition to the spectrum of edge rate transition values, the invention provides a smaller minimal edge rate transition and a substantially larger maximum edge rate transition compared to prior art devices.